FRAMOS Develops New Embedded Vision IP Core for Xilinx FPGAs

FRAMOS has announced that it has developed a new SLVS-EC RX IP Core for easy sensor interfacing with FPGAs from Xilinx. The proprietary FRAMOS FPGA module, available with an EVB, connects SONY’s latest high-speed SLVS-EC interface with Xilinx FPGAs and enables vision engineers to seamlessly upgrade to Sony’s interface technology and to create high-performance vision solutions for unmanned aerial vehicles (UAVs), autonomous cars and other robotics applications. Based on the long-term partnership with Sony and as official Xilinx partner, the FRAMOS IP product provides the technological basis for future camera developments and Embedded Vision devices.

Introduced with the 3rd generation Pregius imagers, SONY’s new high-speed interface standard SLVS-EC is one of the future image sensor interface benchmarks with up to 8 lanes providing 2.3Gbps each, for three to four times higher bandwidths, higher resolutions or a simplified system design comparing to SubLVDS. The FRAMOS-developed RX IP Core reduces overhead and complexity implementing a SONY imager with SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock). As an on-chip function block connecting the customer’s FPGA logic with the image sensor’s data stream, the IP Core receives the interface data, manages the byte-to-pixel conversion for various lane configurations and thus prepares a highly-efficient processing workflow run by the FPGA. The FRAMOS software will support SLVS-EC v1.2 with 1, 2, 4, or 8 lanes configurable by the user and delivers pixels formats from 8 to 14bit of raw data. By de-risking the sensor implementation it significantly reduces the development efforts and accelerates the time to market.

Simon Che’Rose, Head of Development at FRAMOS, explained the advantages for system designers: “SLVS-EC is the benchmark interface standard of the future for high-speed data transfer from SONY imagers. It uplifts existing and upcoming CMOS designs to the next speed and performance level and supports miniaturization. Each customer using SONY image sensors either working with high-speed or embedded solutions will benefit from the SLVS-EC interface and its unique features. Our RX IP Core Block for Xilinx FPGAs in combination with the full documented evaluation kit makes integration and system development easy, resulting in a faster time to market for customer applications working with SLVS-EC.”

The FRAMOS SLVS-EC RX IP core is the first solution for Xilinx FPGAs on the market. The SLVS-EC RX IP Core will work with the main existing and upcoming FPGA families. The package includes the encrypted RTL IP Core with a simulation environment (ModelSim) and dedicated reference implementation examples and supports customers to get up to speed based on FRAMOS’ 37 years imaging experience. The available EVB will provide designs to guide and test the implementation of a SLVS-EC based sensor, including the HW/SW environment and documented implementation examples with sources.

With SLVS-EC, users can benefit from faster sensors with an increased performance, and from a simplified and smaller hardware design by using less lanes. With the Embedded Clock, the interface is robust against clock-skew, allowing larger bandwidth and making dedicated clock lanes obsolete. In industrial applications, FPGAs are a common way to manage sensor control and timing, perform image pre-processing and transform data to common interfaces. SLVS-EC and FPGAs are key to Embedded Vision development and allow high-bandwidth and massive parallel processing capabilities while being flexible and efficient.